Many industrial control systems require high precision and high resolution A/D converters with low or moderate signal bandwidth. Sigma-delta A/D converters often are a cost effective solution for such requirements. In a typical application, a single A/D converter is connected to several external input channels via a multiplexer. One problem associated with converting analog signals in industrial control systems is the filtering of 50-60 Hz line noise. The individual channel throughputs of the converters are adversely impacted by line noise rejection.
Prior art high precision and high resolution sigma-delta A/D converters have multiplexers for receiving a number of external signals. A typical example of one such A/D converter is shown in U.S. Pat. No. 5,345,236. In that patent there is described a multiplexed sigma-delta A/D converter which uses averaging in order to reject line noise and improve converter throughput. So, the A/D converter separates the filtering of high frequency noise from low frequency (50/60 HZ) line noise and the high frequency noise is separately removed by a digital low pass filter. The 50/60 Hz line noise is removed by averaging each of the input channels. The averaging takes place over the typical 50/60 Hz line noise cycle. So long as the external channels are sampled at least once during each line noise quarter cycle, and so long as the sampling occurs at corresponding equally spaced time slots, line noise will be averaged out of each of the sampled external input channels. In this way, high frequency noise is removed by one filter and 50/60 Hz line noise is removed by the averaging operation so long as the conversion operation takes place within an envelope defined by the line noise, i.e. 50/60 Hz.
One of the drawbacks with such a system is that the overall throughput of any given channel is limited to 240 Hz, i.e. four (4) conversions during a cycle of a 60 Hz line or 200 Hz for 50 Hz line noise. It is often desireable to have a higher throughput, but prior art devices are limited by the restraint of equally sampling each channel during the line noise quarter cycle.